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ltc2631 1 2631fc for more information www.linear.com/ltc2631 block diagram features applications description single 12-/10-/8-bit i 2 c v out dacs with 10ppm/c reference the lt c ? 2631 is a family of 12-, 10-, and 8- bit voltage- output dacs with an integrated, high accuracy, low-drift reference in an 8- lead tsot-23 package. it has a rail - to - rail output buffer that is guaranteed monotonic. the ltc2631-l has a full-scale output of 2.5 v, and oper- ates from a single 2.7 v to 5.5 v supply. the ltc2631-h has a full-scale output of 4.096 v, and operates from a 4.5 v to 5.5 v supply. a 10 ppm/c reference output is available at the ref pin. each dac can also operate in external reference mode, in which a voltage supplied to the ref pin sets the full- scale output. the ltc2631 dacs use a 2- wire, i 2 c-compatible serial interface. the ltc2631 operates in both the standard mode ( clock rate of 100 khz) and the fast mode ( clock rate of 400khz). the ltc2631 incorporates a power - on reset circuit . op-tions are available for reset to zero-scale or reset to mid-scale after power-up. integral nonlinearity (ltc2631a-lm12) n integrated precision reference 2.5 v full-scale 10ppm/c (ltc2631-l) 4.096 v full- scale 10ppm/c (ltc2631-h) n maximum inl error: 1lsb (ltc2631a-12) n bidirectional reference: input or 10ppm/c output n 400 khz i 2 c ? interface n nine selectable addresses (ltc2631-z) n low noise (0.7mv p-p , 0.1hz to 200khz) n guaranteed monotonic over temperature n 2.7v to 5.5v supply range (ltc2631-l) n low power operation: 180a at 3v n power down to 1.8a maximum (c and i grades) n power-on reset to zero or mid-scale options n double-buffered data latches n guaranteed operation from C 40 c to 125 c ( h- grade ) n 8-lead tsot-23 (thinsot?) package n mobile communications n process control and industrial automation n automatic test equipment n portable equipment n automotive n optical networking l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and i 2 c and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5396245, 5859606, 6891433, 6937178 and 7414561. (ltc2631-m) dac register resistor divider internal reference input register i 2 c interface dac v out switch control decode logic sda v cc ref gnd dacref 2631 ta01 scl ca0 ref_sel i 2 c address decode code 0 inl (lsb) 0 0.5 4095 2631 ta01b C0.5 C1.0 1024 2048 3072 1.0 v cc = 3v v fs = 2.5v downloaded from: http:///
ltc2631 2 2631fc for more information www.linear.com/ltc2631 absolute maximum ratings supply voltage (v cc ) ................................... C 0.3 v to 6v ref _ sel , scl , sda ..................................... C 0.3 v to 6v v out , ca 0, ca 1, ref ......... C 0.3 v to min (v cc + 0.3 v, 6v) operating temperature range ltc 2631 c ................................................ 0 c to 70 c ltc 2631 i ............................................. C 40 c to 85 c ltc 2631 h ( note 3) ............................ C 40 c to 125 c (notes 1, 2) ca0 1scl 2 sda 3 gnd 4 8 ca17 v out 6 ref5 v cc top view ts8 package 8-lead plastic tsot-23 t jmax = 150c (note 6), ja = 195c/w ca0 1scl 2 sda 3 gnd 4 8 ref_sel7 v out 6 ref5 v cc top view ts8 package 8-lead plastic tsot-23 t jmax = 150c (note 6), ja = 195c/w pin configuration maximum junction temperature .......................... 150 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 300 c ltc2631-z ltc2631-m downloaded from: http:///
ltc2631 3 2631fc for more information www.linear.com/ltc2631 ltc2631 a c ts8 ?l m 12 #trm pbf lead free designator tape and reel tr = 2,500-piece tape and reel trm = 500-piece tape and reel resolution 12 = 12-bit 10 = 10-bit 8 = 8-bit power-on reset m = reset to mid-scale z = reset to zero-scale full-scale volt age, internal reference mode l = 2.5v h = 4.096v package type ts8 = 8-lead plastic tsot-23 tempera ture grade c = commercial temperature range (0c to 70c) i = industrial temperature range (C40c to 85c) h = automotive temperature range (C 40c to 125c) electrical grade (optional) a = 1lsb maximum inl (12-bit) product part number consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ order information downloaded from: http:///
ltc2631 4 2631fc for more information www.linear.com/ltc2631 product selection guide part number par t marking * v fs with internal reference power-on reset to code pin 8 resolution v cc maximum inl ltc2631a-lm12ltc2631a-lz12 ltc2631a-hm12 ltc2631a-hz12 ltdhf l tdhg ltdhh ltdhj 2.5v ? (4095/4096)2.5v ? (4095/4096) 4.096v ? (4095/4096) 4.096v ? (4095/4096) mid-scalezero mid-scale zero ref_selca1 ref_sel ca1 12-bit12-bit 12-bit 12-bit 2.7v C 5.5v2.7v C 5.5v 4.5v C 5.5v 4.5v C 5.5v 1lsb1lsb 1lsb 1lsb ltc2631-lm12ltc2631-lm10 ltc2631-lm8 ltdhf ltdhk ltdhq 2.5v ? (4095/4096)2.5v ? (1023/1024) 2.5v ? (255/256) mid-scalemid-scale mid-scale ref_selref_sel ref_sel 12-bit10-bit 8-bit 2.7v C 5.5v2.7v C 5.5v 2.7v C 5.5v 2.5lsb1lsb 0.5lsb ltc2631-lz12ltc2631-lz10 ltc2631-lz8 ltdhg ltdhm ltdhr 2.5v ? (4095/4096)2.5v ? (1023/1024) 2.5v ? (255/256) zerozero zero ca1ca1 ca1 12-bit10-bit 8-bit 2.7v C 5.5v2.7v C 5.5v 2.7v C 5.5v 2.5lsb1lsb 0.5lsb ltc2631-hm12ltc2631-hm10 ltc2631-hm8 ltdhh ltdhn ltdhs 4.096v ? (4095/4096)4.096v ? (1023/1024) 4.096v ? (255/256) mid-scalemid-scale mid-scale ref_selref_sel ref_sel 12-bit10-bit 8-bit 4.5v C 5.5v4.5v C 5.5v 4.5v C 5.5v 2.5lsb1lsb 0.5lsb ltc2631-hz12ltc2631-hz10 ltc2631-hz8 ltdhj ltdhp ltdht 4.096v ? (4095/4096)4.096v ? (1023/1024) 4.096v ? (255/256) zerozero zero ca1ca1 ca1 12-bit10-bit 8-bit 4.5v C 5.5v4.5v C 5.5v 4.5v C 5.5v 2.5lsb1lsb 0.5lsb *the temperature grade is identified by a label on the shipping container. downloaded from: http:///
ltc2631 5 2631fc for more information www.linear.com/ltc2631 electrical characteristics ltc2631-8 ltc2631-10 ltc2631-12 ltc2631a-12 symbol parameter conditions min typ max min typ max min typ max min typ max units dc performance resolution l 8 10 12 12 bits monotonicity v cc = 3v, internal ref. (note 4) l 8 10 12 12 bits dnl differential nonlinearity v cc = 3v, internal ref. (note 4) l 0.5 0.5 1 1 lsb inl integral nonlinearity v cc = 3v, internal ref. (note 4) l 0.05 0.5 0.2 1 1 2.5 0.5 1 lsb zse zero-scale error v cc = 3v, internal ref., code = 0 l 0.5 5 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 3v, internal ref. (note 5) l 0.5 5 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coefficient v cc = 3v, internal ref. (note 5) 10 10 10 10 v/c fse full-scale error v cc = 3v, internal ref. (note 15) l 0.08 0.4 0.08 0.4 0.08 0.4 0.08 0.4 %fsr v fstc full-scale voltage temperature coefficient v cc = 3 v , internal ref . ( note 10) c-grade i-grade h-grade 10 10 10 10 10 10 10 10 10 10 10 10 ppm/c ppm/c ppm/c load regulation internal ref., mid-scale, v cc = 3v 10%, C5ma i out 5ma, v cc = 5v 10%, C10ma i out 10ma l l 0.009 0.009 0.016 0.016 0.035 0.035 0.064 0.064 0.14 0.14 0.256 0.256 0.14 0.14 0.256 0.256 lsb / ma lsb / ma r out dc output impedance internal ref., mid-scale, v cc = 3v 10%, C5ma i out 5ma, v cc = 5v 10%, C10ma i out 10ma l l 0.09 0.09 0.156 0.156 0.09 0.09 0.156 0.156 0.09 0.09 0.156 0.156 0.09 0.09 0.156 0.156 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specified. ltc2631-lm12/-lm10/-lm8/-lz12/-lz10/-lz8, ltc2631a-lm12/-lz12 (v fs = 2.5v) symbol parameter conditions min typ max units v out dac output span external reference internal reference 0 to v ref 0 to 2.5 v v psr power supply rejection v cc = 3v 10% or 5v 10% C80 db i sc short-circuit output current (note 6) sinking sourcing v fs = v cc = 5.5v zero-scale; v out shorted to v cc full-scale; v out shorted to gnd l l 27 C28 48 C48 ma ma power supply v cc positive supply voltage for specified performance l 2.7 5.5 v i cc supply current (note 7) v cc = 3v, v ref = 2.5v, external reference v cc = 3v, internal reference v cc = 5v, v ref = 2.5v, external reference v cc = 5v, internal reference l l l l 150 180 160 190 200 240 210 260 a a a a i sd supply current in power-down mode (note 7) v cc = 5v, c-grade, i-grade v cc = 5v, h-grade l l 0.6 0.6 1.8 4 a a downloaded from: http:///
ltc2631 6 2631fc for more information www.linear.com/ltc2631 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specified. ltc2631-lm12/-lm10/-lm8/-lz12/-lz10/-lz8, ltc2631a-lm12/-lz12 (v fs = 2.5v) symbol parameter conditions min typ max units reference input input voltage range l 0 v cc v resistance l 160 190 220 k capacitance 7.5 pf i ref reference current, power-down mode dac powered down l 0.005 0.1 a reference output output voltage l 1.240 1.250 1.260 v reference temperature coefficient 10 ppm/c output impedance 0.5 k capacitive load driving 10 f short-circuit current v cc = 5.5v; ref shorted to gnd 2.5 ma digital i/ov il low level input voltage (sda and scl) (note 14) l C0.5 0.3v cc v v ih high level input voltage (sda and scl) (note 11) l 0.7v cc v v il(ca n ) low level input voltage on ca n (n = 0, 1) see test cir cuit 1 l 0.15v cc v v ih(ca n ) high level input voltage on ca n (n = 0, 1) see test cir cuit 1 l 0.85v cc v r inh resistance from ca n (n = 0, 1) to v cc to set ca n = v cc see test circuit 2 l 10 k r inl resistance from ca n (n = 0, 1) to gnd to set ca n = gnd see test circuit 2 l 10 k r inf resistance from ca n (n = 0, 1) to v cc or gnd to set ca n = float see test circuit 2 l 2 m v ol low level output voltage sink current = 3ma l 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 12) l 20 + 0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 0 50 ns i in input leakage 0.1v cc v in 0.9v cc l 1 a c in i/o pin capacitance (note 8) l 10 pf c b capacitive load for each bus line l 400 pf c ca n external capacitive load on address pin ca n (n = 0, 1) l 10 pf downloaded from: http:///
ltc2631 7 2631fc for more information www.linear.com/ltc2631 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specified. ltc2631-lm12/-lm10/-lm8/-lz12/-lz10/-lz8, ltc2631a-lm12/-lz12 (v fs = 2.5v) symbol parameter conditions min typ max units ac performancet s settling time v cc = 3v (note 9) 0.39% (1lsb at 8-bits) 0.098% (1lsb at 10-bits) 0.024% (1lsb at 12-bits) 3.2 3.8 4.1 s s s voltage-output slew rate 1 v/s capacitance load driving 500 pf glitch impulse at mid-scale transition 2.1 nv?s multiplying bandwidth external reference 300 khz e n output voltage noise density at f = 1khz, external reference at f = 10khz, external reference at f = 1khz, internal reference at f = 10khz, internal reference 140 130 160 150 nv hz nv hz nv hz nv hz output voltage noise 0.1hz to 10hz, external reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, external reference 0.1hz to 200khz, internal reference, c ref = 0.33f 20 20 650 670 v p-p v p-p v p-p v p-p timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v. (see figure 1) (note 13). ltc2631-lm12/-lm10/-lm8/-lz12/-lz10/-lz8, ltc2631a-lm12/-lz12 (v fs = 2.5v) symbol parameter conditions min typ max units f scl scl clock frequency l 0 400 khz t hd( sta ) hold time (repeated) start condition l 0.6 s t low low period of the scl clock pin l 1.3 s t high high period of the scl clock pin l 0.6 s t su( sta ) set-up time for a repeated start condition l 0.6 s t hd( dat ) data hold time l 0 0.9 s t su( dat ) data set-up time l 100 ns t r rise time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t f fall time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s downloaded from: http:///
ltc2631 8 2631fc for more information www.linear.com/ltc2631 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise specified. ltc2631-hm12/-hm10/-hm8/-hz12/-hz10/-hz8, ltc2631a-hm12/-hz12 (v fs = 4.096v) ltc2631-8 ltc2631-10 ltc2631-12 ltc2631a-12 symbol parameter conditions min typ max min typ max min typ max min typ max units dc performance resolution l 8 10 12 12 bits monotonicity v cc = 5v, internal ref. (note 4) l 8 10 12 12 bits dnl differential nonlinearity v cc = 5v, internal ref. (note 4) l 0.5 0.5 1 1 lsb inl integral nonlinearity v cc = 5v, internal ref. (note 4) l 0.05 0.5 0.2 1 1 2.5 0.5 1 lsb zse zero-scale error v cc = 5v, internal ref., code = 0 l 0.5 5 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 5v, internal ref. (note 5) l 0.5 5 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coefficient v cc = 5v, internal ref. (note 5) 10 10 10 10 v/c fse full-scale error v cc = 5v, internal ref. (note 15) l 0.08 0.4 0.08 0.4 0.08 0.4 0.08 0.4 %fsr v fstc full-scale voltage temperature coefficient v cc = 5v, internal ref. (note 10) c-grade i-grade h-grade 10 10 10 10 10 10 10 10 10 10 10 10 ppm/c ppm/c ppm/c load regulation v cc = 5v 10%, internal ref. mid - scale , C10 ma i out 10 ma l 0.006 0.01 0.022 0.04 0.09 0.16 0.09 0.16 lsb / ma r out dc output impedance v cc = 5v 10%, internal ref. mid - scale , C10 ma i out 10 ma l 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 symbol parameter conditions min typ max units v out dac output span external reference internal reference 0 to v ref 0 to 4.096 v v psr power supply rejection v cc = 5v 10% C80 db i sc short-circuit output current (note 6) sinking sourcing v fs = v cc = 5.5v zero-scale; v out shorted to v cc full-scale; v out shorted to gnd l l 27 C28 48 C48 ma ma power supplyv cc positive supply voltage for specified performance l 4.5 5.5 v i cc supply current (note 7) v cc = 5v, v ref = 4.096v, external reference v cc = 5v, internal reference l l 160 200 220 270 a a i sd supply current in power-down mode (note 7) v cc = 5v, c-grade, i-grade v cc = 5v, h-grade l l 0.6 0.6 1.8 4 a a downloaded from: http:///
ltc2631 9 2631fc for more information www.linear.com/ltc2631 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise specified. ltc2631-hm12/-hm10/-hm8/-hz12/-hz10/-hz8, ltc2631a-hm12/-hz12 (v fs = 4.096v) symbol parameter conditions min typ max units reference input input voltage range l 0 v cc v resistance l 160 190 220 k capacitance 7.5 pf i ref reference current, power-down mode dac powered down l 0.005 0.1 a reference output output voltage l 2.032 2.048 2.064 v reference temperature coefficient 10 ppm/c output impedance 0.5 k capacitive load driving 10 f short-circuit current v cc = 5.5v; ref shorted to gnd 4.3 ma digital i/ov il low level input voltage (sda and scl) (note 14) l C0.5 0.3v cc v v ih high level input voltage (sda and scl) (note 11) l 0.7v cc v v il(ca n ) low level input voltage on ca n (n = 0, 1) see test cir cuit 1 l 0.15v cc v v ih(ca n ) high level input voltage on ca n (n = 0, 1) see test cir cuit 1 l 0.85v cc v r inh resistance from ca n (n = 0, 1) to v cc to set ca n = v cc see test circuit 2 l 10 k r inl resistance from ca n (n = 0, 1) to gnd to set ca n = gnd see test circuit 2 l 10 k r inf resistance from ca n (n = 0, 1) to v cc or gnd to set ca n = float see test circuit 2 l 2 m v ol low level output voltage sink current = 3ma l 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 12) l 20 + 0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 0 50 ns i in input leakage 0.1v cc v in 0.9v cc l 1 a c in i/o pin capacitance (note 8) l 10 pf c b capacitive load for each bus line l 400 pf c ca n external capacitive load on address pin ca n (n = 0, 1) l 10 pf downloaded from: http:///
ltc2631 10 2631fc for more information www.linear.com/ltc2631 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise specified. ltc2631-hm12/-hm10/-hm8/-hz12/-hz10/-hz8, ltc2631a-hm12/-hz12 (v fs = 4.096v) symbol parameter conditions min typ max units ac performancet s settling time v cc = 5v (note 9) 0.39% (1lsb at 8-bits) 0.098% (1lsb at 10-bits) 0.024% (1lsb at 12-bits) 3.7 4.2 4.6 s s s voltage-output slew rate 1 v/s capacitance load driving 500 pf glitch impulse at mid-scale transition 3.0 nv?s multiplying bandwidth external reference 300 khz e n output voltage noise density at f = 1khz, external reference at f = 10khz, external reference at f = 1khz, internal reference at f = 10khz, internal reference 140 130 210 200 nv hz nv hz nv hz nv hz output voltage noise 0.1hz to 10hz, external reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, external reference 0.1hz to 200khz, internal reference, c ref = 0.33f 20 20 650 670 v p-p v p-p v p-p v p-p downloaded from: http:///
ltc2631 11 2631fc for more information www.linear.com/ltc2631 timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 4.5v to 5.5v. (see figure 1) (note 13). ltc2631-hm12/-hm10/-hm8/-hz12/-hz10/-hz8, ltc2631a-hm12/-hz12 (v fs = 4.096v) symbol parameter conditions min typ max units f scl scl clock frequency l 0 400 khz t hd( sta ) hold time (repeated) start condition l 0.6 s t low low period of the scl clock pin l 1.3 s t high high period of the scl clock pin l 0.6 s t su( sta ) set-up time for a repeated start condition l 0.6 s t hd( dat ) data hold time l 0 0.9 s t su( dat ) data set-up time l 100 ns t r rise time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t f fall time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are with respect to gnd. note 3: high temperatures degrade operating lifetimes. operating lifetime is derated at temperatures greater than 105c.note 4: linearity and monotonicity are defined from code k l to code 2 n C 1, where n is the resolution and k l is given by k l = 0.016 ? (2 n / v fs ), rounded to the nearest whole code. for v fs = 2.5v and n = 12, k l = 26 and linearity is defined from code 26 to code 4,095. for v fs = 4.096v and n = 12, k l = 16 and linearity is defined from code 16 to code 4,095. note 5: inferred from measurement at code 16 (ltc2631-12), code 4 (ltc2631-10) or code 1 (ltc2631-8), and at full-scale.note 6: this ic includes current limiting that is intended to protect the device during momentary overload conditions. junction temperature can exceed the rated maximum during current limiting. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 7: digital inputs at 0v or v cc . note 8: guaranteed by design and not production tested. note 9: internal reference mode. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k in parallel with 100pf to gnd.note 10: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range.note 11: maximum v ih = v cc(max) + 0.5v note 12: c b = capacitance of one bus line in pf note 13: all values refer to v ih = v ih(min) and v il = v il(max) levels. note 14: minimum v il exceeds the absolute maximum rating. this condition wont damage the ic, but could degrade performance. note 15: full-scale error is determined using the reference voltage measured at the ref pin. downloaded from: http:///
ltc2631 12 2631fc for more information www.linear.com/ltc2631 typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) reference output voltage vs temperature dnl vs temperature full-scale output voltage vs temperature settling to 1lsb settling to 1lsb ltc2631-l12 (internal reference, v fs = 2.5v) inl vs temperature code 0 inl (lsb) 0 0.5 4095 2631 g01 C0.5C1.0 1024 2048 3072 1.0 v cc = 3v code 0 dnl (lsb) 0 0.5 4095 2631 g02 C0.5C1.0 1024 v cc = 3v 2048 3072 1.0 temperature (c) C50 C25 25 75 125 v ref (v) 1.250 1.255 150 2631 g03 1.2451.240 0 50 100 1.260 v cc = 3v temperature (c) C50 C25 25 75 125 inl (lsb) 0 0.5 150 2631 g04 C0.5C1.0 0 50 100 1.0 v cc = 3v inl (pos) inl (neg) temperature (c) C50 C25 25 75 125 dnl (lsb) 0 0.5 150 2631 g05 C0.5C1.0 0 50 100 1.0 v cc = 3v dnl (pos) dnl (neg) temperature (c) C50 C25 25 75 125 fs output voltage (v) 2.50 2.51 150 2631 g06 2.492.48 0 50 100 2.52 v cc = 3v 2s/div 2631 g07 v out 1lsb/div 1/4 scale to 3/4 scale stepv cc = 3v, v fs = 2.5v r l = 2k, c l = 100pf average of 256 events scl 2v/div 3.6s 9th clock of 3rd data byte 2s/div 2631 g08 v out 1lsb/div 3/4 scale to 1/4 scale stepv cc = 3v, v fs = 2.5v r l = 2k, c l = 100pf average of 256 events scl 2v/div 4.1s 9th clock of 3rd data byte t a = 25c, unless otherwise noted. downloaded from: http:///
ltc2631 13 2631fc for more information www.linear.com/ltc2631 typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) reference output voltage vs temperature dnl vs temperature full-scale output voltage vs temperature settling to 1lsb settling to 1lsb ltc2631-h12 (internal reference, v fs = 4.096v) inl vs temperature temperature (c) C50 C25 25 75 125 inl (lsb) 0 0.5 150 2631 g12 C0.5C1.0 0 50 100 1.0 v cc = 5v inl (pos) inl (neg) temperature (c) C50 C25 25 75 125 dnl (lsb) 0 0.5 150 2631 g13 C0.5C1.0 0 50 100 1.0 v cc = 5v dnl (pos) dnl (neg) temperature (c) C50 C25 25 75 125 fs output voltage (v) 4.095 4.105 150 2631 g14 4.0854.075 0 50 100 4.115 v cc = 5v code 0 inl (lsb) 0 0.5 4095 2631 g09 C0.5C1.0 1024 2048 3072 1.0 v cc = 5v code 0 dnl (lsb) 0 0.5 4095 2631 g10 C0.5C1.0 1024 2048 3072 1.0 v cc = 5v temperature (c) C50 C25 25 75 125 v ref (v) 2.048 2.058 150 2631 g11 2.0382.028 0 50 100 2.068 v cc = 5v 2s/div 2631 g15 v out 1lsb/div 1/4 scale to 3/4 scale stepv cc = 5v, v fs = 4.095v r l = 2k, c l = 100pf average of 256 events scl 5v/div 3.9s 9th clock of 3rd data byte 2s/div 2631 g16 v out 1lsb/div scl 5v/div 4.6s 3/4 scale to 1/4 scale stepv cc = 5v, v fs = 4.095v r l = 2k, c l = 100pf average of 256 events 9th clock of 3rd data byte t a = 25c, unless otherwise noted. downloaded from: http:///
ltc2631 14 2631fc for more information www.linear.com/ltc2631 typical performance characteristics ltc2631-10 integral nonlinearity (inl) differential nonlinearity (dnl) integral nonlinearity (inl) differential nonlinearity (dnl) load regulation current limiting ltc2631-8ltc2631 code 0 inl (lsb) 0 0.5 1023 2631 g17 C0.5C1.0 256 512 768 1.0 v cc = 5v v fs = 4.096v internal ref. code 0 dnl (lsb) 0 0.5 1023 2631 g18 C0.5C1.0 256 512 768 1.0 v cc = 5v v fs = 4.096v internal ref. code 0 inl (lsb) 0 0.5 255 2631 g19 C0.5C1.0 64 128 192 1.0 v cc = 3v v fs = 2.5v internal ref. code 0 dnl (lsb) 0 0.25 255 2631 g20 C0.25C0.50 64 128 192 0.50 v cc = 3v v fs = 2.5v internal ref. i out (ma) C30 C20 C10 0 10 20 30 v out (mv) 0 2 4 6 8 2631 g21 C6 C4 C2C8 C10 10 internal ref. code = midscale v cc = 5v (ltc2631-h) v cc = 5v (ltc2631-l) v cc = 3v (ltc2631-l) i out (ma) C30 C20 C10 0 10 20 30 ? v out (v) C0.05 0 0.05 0.10 0.15 2631 g22 C0.20 C0.15 C0.10 0.20 internal ref. code = midscale v cc = 5v (ltc2631-h) v cc = 5v (ltc2631-l) v cc = 3v (ltc2631-l) t a = 25c, unless otherwise noted. downloaded from: http:///
ltc2631 15 2631fc for more information www.linear.com/ltc2631 typical performance characteristics ltc2631 offset error vs temperature large-signal response headroom at rails vs output current exiting power-down to mid-scale mid-scale-glitch impulse power-on reset glitch temperature (c) C50 C25 0 25 50 75 100 125 150 offset error (mv) 0 1 2 2631 g23 C1C2 C3 3 i out (ma) 0 1 2 3 4 5 6 7 8 9 10 v out (v) 2.52.0 3.53.0 4.0 2631 g29 1.51.0 0.5 0 5.04.5 3v (ltc2631-l) sourcing 3v (ltc2631-l) sinking 5v sourcing 5v sinking 2s/div v out 0.5v/div 2631 g26 v fs = v cc = 5v 1/4 scale to 3/4 scale 2s/div v out 5mv/div 2631 g27 scl 5v/div ltc2631-l12, v cc = 3v: 2.1nv-s typ ltc2631-h12, v cc = 5v: 3.0nv-s typ 9th clock of 3rd data byte 200s/div v cc 2v/div 2631 g28 ltc2631-l v out 2mv/div zero-scale 4s/div 2631 g30 ltc2631-h cs /ld 2v/div v out 0.5v/div v cc (v) 2.5 3 3.5 4 4.5 5 5.5 gain error (%fsr) 0.1 0.2 0.3 2631 g24 0.0 C0.3 C0.2 C0.1C0.4 0.4 external ref. v ref = 2.5v gain error vs v cc gain error vs temperature temperature (c) C50 C25 0 25 50 75 100 125 150 gain error (%fsr) 0.1 0.2 0.3 2631 g25 0.0 C0.3 C0.2 C0.1C0.4 0.4 external ref. v ref = 2.5v t a = 25c, unless otherwise noted. downloaded from: http:///
ltc2631 16 2631fc for more information www.linear.com/ltc2631 typical performance characteristics ltc2631 multiplying bandwidth noise voltage vs frequency 0.1hz to 10hz voltage noise supply current vs logic voltage supply current vs ref_sel voltage frequency (hz) 100 noise voltage (nv /hz) 200 300 1m 2631 g34 100 0 1k 10k 100k 500400 internal ref. code = midscale ltc2631-h (v cc = 5v) ltc2631-l (v cc = 4v) 1s/div 10v/div 2631 g35 ltc2631-l, v cc = 4v internal ref. code = midscale logic voltage (v) 0 i cc (ma) 1.2 0.80.4 1.00.6 0.2 0.0 4 2 2631 g31 5 3 1 v cc = 5v v cc = 3v (ltc2631-l) sweep scl and sda between 0v and v cc ref_sel voltage (v) 0 i cc (ma) 0.5 0.3 0.40.2 0.1 4 2 2631 g32 5 3 1 v cc = 5v v cc = 3v (ltc2631-l) sweep ref_sel between 0v and v cc frequency (hz) 1k db 0 C2C6 C8 C14 C4 C12 C10C16 C18 100k 2631 g33 1000k 10k v cc = 5v v ref(dc) = 2v v ref(ac) = 0.2v p-p code = full scale t a = 25c, unless otherwise noted. downloaded from: http:///
ltc2631 17 2631fc for more information www.linear.com/ltc2631 pin functions ca 0 ( pin 1): chip address bit 0. tie this pin to v cc , gnd or leave it floating to select an i 2 c slave address for the part (see tables 1 and 2). scl ( pin 2): serial clock input pin. data is shifted into the sda pin at the rising edges of the clock. this high impedance pin requires a pull-up resistor or current source to v cc . sda ( pin 3): serial data bidirectional pin. data is shifted into the sda pin and acknowledged by the sda pin. this pin is high impedance while data is shifted in. open-drain n-channel output during acknowledgment. sda requires a pull-up resistor or current source to v cc . gnd (pin 4): ground. v cc ( pin 5): supply voltage input . 2.7 v v cc 5.5 v (ltc2631-l) or 4.5 v v cc 5.5 v ( ltc2631-h). bypass to gnd with a 0.1f capacitor. ref ( pin 6): reference voltage input or output. when external reference mode is selected, ref is an input (0 v v ref v cc ) where the voltage supplied sets the full- scale voltage. when internal reference is selected, the 10ppm/c 1.25 v ( ltc2631-l) or 2.048 v ( ltc2631-h) internal reference is available at the pin. this output may be bypassed to gnd with up to 10 f (0.33 f is recom- mended), and must be buffered when driving external dc load current.v out (pin 7): dac analog voltage output. ca 1 ( pin 8, ltc2631-z): chip address bit 1. tie this pin to v cc , gnd or leave it floating to select an i 2 c slave ad- dress for the part (see table 1). ref_sel ( pin 8, ltc2631-m): selects default reference at power up. tie to v cc to select the internal reference, or gnd to select an external reference. after power-up, the logic state at this pin is ignored and the reference may be changed only by software command. downloaded from: http:///
ltc2631 18 2631fc for more information www.linear.com/ltc2631 block diagrams dac register resistor divider internal reference input register i 2 c interface dac v out switch control decode logic sda v cc ref gnd dacref 2631 bd scl ca0 ref_sel i 2 c address decode dac register resistor divider internal reference input register i 2 c interface dac v out switch control decode logic sda v cc ref gnd dacref scl ca1 ca0 i 2 c address decode test circuits ltc2631-z ltc2631-m 100? r inh /r inl /r inf v ih(ca n ) /v il(ca n ) ca n gnd 2631 tc v cc test circuit 2 test circuit 1 ca n test circuits for i 2 c digital i/o (see electrical characteristics) downloaded from: http:///
ltc2631 19 2631fc for more information www.linear.com/ltc2631 timing diagrams figure 1. serial interface timing figure 2. typical ltc2631 write transaction sda t f s t r t low t hd(sta) all voltage levels refer to v ih(min) and v il(max) levels t hd(dat) t su(dat) t su(sta) t hd(sta) t su(sto) t sp t buf t r t f t high scl s p s 2631 f01 ack ack 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 2631 f02 ack start sda a6 a5 a4 a3 slave address a2 a1 a0 w scl c2 c3 c1 c0 x x x x x x x x ack 1st data byte 2nd data byte 3rd data byte downloaded from: http:///
ltc2631 20 2631fc for more information www.linear.com/ltc2631 operation the ltc2631 is a family of single voltage-output dacs in 8- lead thinsot packages. each dac can operate rail- to-rail using an external reference, or with its full-scale voltage set by an integrated reference. twelve combina - tions of accuracy (12-, 10-, and 8- bit), power-on reset value ( zero or mid-scale), and full-scale voltage (2.5 v or 4.096v) are available. the ltc2631 is controlled using a 2-wire i 2 c interface. power-on reset the ltc2631-hz/ltc2631-lz clear the output to zero- scale when power is first applied, making system initial - ization consistent and repeatable. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2631 contains circuitry to reduce the power-on glitch: the ana - log output typically rises less than 5 mv above zero-scale during power on if the power supply is ramped to 5 v in 1ms or more. in general, the glitch amplitude decreases as the power supply ramp time is increased. see power-on reset glitch in the typical performance characteristics section. the ltc2631-hm/ltc2631-lm provide an alternative reset, setting the output to mid-scale when power is first applied. default reference mode selection is described in the ref- erence modes section.power supply sequencing the voltage at ref ( pin 6) should be kept within the range C 0.3 v v ref v cc + 0.3 v ( see absolute maximum rat- ings). particular care should be taken to observe these limits during power supply turn - on and turn - off sequences , when the voltage at v cc (pin 5) is in transition. transfer function the digital-to-analog transfer function is v out(ideal) = k 2 n ? ? ? ? ? ? v ref where k is the decimal equivalent of the binary dac input code, n is the resolution, and v ref is either 2.5 v ( ltc2631 - lm/ltc2631-lz) or 4.096 v ( ltc2631-hm/ltc2631-hz) when in internal reference mode, and the voltage at ref (pin 6) when in external reference mode.i 2 c serial interface the ltc2631 communicates with a host using the stan- dard 2- wire i 2 c interface. the timing diagrams ( figures 1 and 2) show the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the value of these pull-up resistors is dependent on the power supply and can be obtained from the i 2 c specifications. for an i 2 c bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pf. the ltc2631 is a receive-only ( slave) device. the master can write to the ltc2631. the ltc2631 does not respond to a read from the master. start (s) and stop (p) conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a communi- cation to a slave device by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop condition. a stop condition is generated by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. acknowledge the acknowledge signal is used for handshaking between the master and the slave. an acknowledge ( active low) generated by the slave lets the master know that the latest byte of information was properly received. the acknowl - edge related clock pulse is generated by the master. the master releases the sda line ( high) during the acknowl- edge clock pulse. the slave-receiver must pull down the sda bus line during the acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. the ltc2631 responds to a write by a master downloaded from: http:///
ltc2631 21 2631fc for more information www.linear.com/ltc2631 operation in this manner but does not acknowledge a read operation; in that case, sda is retained high during the period of the acknowledge clock pulse. chip address the state of pins ca0 and ca 1 ( ltc2631-hz/ltc2631- lz) determines the slave address of the part. these pins can each be set to any one of three states: v cc , gnd or float. this results in nine ( ltc2631-hz/ltc2631-lz) or three ( ltc2631-hm/ltc2631-lm) selectable addresses for the part. the slave address assignments are shown in tables 1 and 2. table 1. slave address map (ltc2631-z) ca1 ca0 a6 a5 a4 a3 a2 a1 a0 gnd gnd 0 0 1 0 0 0 0 gnd float 0 0 1 0 0 0 1 gnd v cc 0 0 1 0 0 1 0 float gnd 0 0 1 0 0 1 1 float float 0 1 0 0 0 0 0 float v cc 0 1 0 0 0 0 1 v cc gnd 0 1 0 0 0 1 0 v cc float 0 1 0 0 0 1 1 v cc v cc 0 1 1 0 0 0 0 global address 1 1 1 0 0 1 1 table 2. slave address map (ltc2631-m) ca0 a6 a5 a4 a3 a2 a1 a0 gnd 0 0 1 0 0 0 0 float 0 0 1 0 0 0 1 v cc 0 0 1 0 0 1 0 global address 1 1 1 0 0 1 1 in addition to the address selected by the address pins, the part also responds to a global address. this address allows a common write to all ltc2631 parts to be accom - plished using one 3- byte write transaction on the i 2 c bus. the global address, listed at the end of tables 1 and 2, is a 7- bit hardwired address not selectable by ca0/ca1. if another address is required, please consult the factory. the maximum capacitive load allowed on the ca0/ca1 address pins is 10 pf, as these pins are driven during ad- dress detection to determine if they are floating. write word protocol the master initiates communication with the ltc2631 with a start condition and a 7- bit slave address followed by the write bit ( w ) = 0. the ltc2631 acknowledges by pulling the sda pin low at the ninth clock if the 7- bit slave address matches the address of the part ( set by ca0/ca1) or the global address. the master then transmits 3- bytes of data. the ltc2631 acknowledges each byte of data by pulling the sda line low at the ninth clock of each data byte transmission. after receiving three complete bytes of data, the ltc2631 executes the command specified in the 24-bit input word. if more than three data bytes are transmitted after a valid 7-bit slave address, the ltc2631 does not acknowledge the extra bytes of data ( sda is high during the 9 th clock). the format of the three data bytes is shown in figure 3. the first byte of the input word consists of the 4- bit com - mand, followed by four don t- cares bits. the next two bytes contain the 16- bit data word, which consists of the 12-, 10- or 8- bit input code, msb to lsb, followed by 4, 6 or 8 don t- cares bits ( ltc2631-12, ltc2631-10 and ltc2631-8 respectively). a typical ltc2631 write transaction is shown in figure 4. the command bit assignments ( c3-c0) are shown in table 3. the first four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32- bit shift register into the input register. in an update operation, the data word is copied from the input register to the dac register and converted to an analog voltage at the dac output. the update operation also powers up the dac if it had been in power-down mode. the data path and registers are shown in the block diagram. downloaded from: http:///
ltc2631 22 2631fc for more information www.linear.com/ltc2631 operation table 3. command codes command* c3 c2 c1 c0 0 0 0 0 write to input register 0 0 0 1 update (power up) dac register 0 0 1 1 write to and update (power up) dac register 0 1 0 0 power down 0 1 1 0 select internal reference 0 1 1 1 select external reference *command codes not shown are reserved and should not be used. reference modesfor applications where an accurate external reference is not available, the ltc2631 has a user-selectable, integrated reference. the ltc2631-lm/ltc2631-lz provide a full- scale output of 2.5 v . the ltc2631 - hm / ltc2631 - hz provide a full - scale output of 4.096 v . the internal reference can be useful in applications where the supply voltage is poorly regulated. internal reference mode can be selected by using command 0110, and is the power-on default for ltc2631-hz/ltc2631-lz, as well as for ltc2631-hm/ ltc2631-lm when ref_sel is tied high. the 10 ppm/ c , 1.25 v ( ltc2631 - lm / ltc2631 - lz) or 2.048v ( ltc2631-hm/ltc2631-hz) internal reference is available at the ref pin. adding bypass capacitance to the ref pin will improve noise performance ; 0.33 f is recommended, and up to 10 f can be driven without oscillation. this output must be buffered when driving external dc load current. alternatively, the dac can operate in external reference mode using command 0111. in this mode, an input voltage supplied externally to the ref pin provides the reference (0 v v ref v cc ) and the supply current is reduced. external reference mode is the power-on default for ltc2631-hm/ ltc2631-lm when ref_sel is tied low. the reference mode of ltc2631-hz/ltc2631-lz can be changed only by software command. the same is true for ltc2631-hm/ltc2631-lm after power-on, after which the logic state on ref_sel is ignored. power-down mode for power - constrained applications, the ltc2631 s power - down mode can be used to reduce the supply current whenever the dac output is not needed. when in power down, the buffer amplifier, bias circuit, and reference circuit are disabled and draw essentially zero current. the dac output is put into a high-impedance state, and the output pin is passively pulled to ground through a 200 k resistor. input and dac register contents are not disturbed during power down. figure 3. command and data input format c3 1st data byte input word (ltc2631-12) write word protocol for ltc2631 c2 c1 c0 x x x x d9 d10 d11 s w a slave address 1st data byte d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x a 2nd data byte a 3rd data byte a p 2631 f03 2nd data byte input word 3rd data byte c3 1st data byte input word (ltc2631-10) c2 c1 c0 x x x x d7 d8 d9 d6 d5 d4 d3 d2 d1 d0 x x x x x x 2nd data byte 3rd data byte c3 1st data byte input word (ltc2631-8) c2 c1 c0 x x x x d5 d6 d7 d4 d3 d2 d1 d0 x x x x x x x x 2nd data byte 3rd data byte downloaded from: http:///
ltc2631 23 2631fc for more information www.linear.com/ltc2631 operation the dac can be put into power-down mode by using command 0100. the supply current is reduced to 1.8 a maximum ( c and i grades) and the ref pin becomes high impedance (typically > 1g). normal operation resumes after executing any command that includes a dac update, as shown in table 3. the dac is powered up and its voltage output is updated. normal settling is delayed while the bias, reference, and ampli - fier cir cuits are re-enabled. when the ref pin output is bypassed to gnd with 1 nf or less, the power-up delay time is 20 s for settling to 12- bits. this delay increases to 200s for 0.33f, and 10ms for 10f. voltage output the ltc2631s integrated rail-to-rail amplifier has guar- anteed load regulation when sourcing or sinking up to 10ma at 5v, and 5ma at 3v. load regulation is a measure of the amplifiers ability to maintain the rated voltage accuracy over a wide range of load current. the measured change in output voltage per change in forced load current is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the amplifiers dc output impedance is 0.1 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50 typical channel resistance of the output devices (e.g., when sinking 1ma, the minimum output voltage is 50 ? 1 ma, or 50 mv). see the graph headroom at rails vs. output current in the typical performance charac- teristics section. the amplifier is stable driving capacitive loads of up to 500pf. rail-to-rail output considerations in any rail-to-rail voltage-output device, the output is lim- ited to voltages within the supply range.since the analog output of the dac cannot go below ground , it may limit the lowest codes, as shown in figure 5 b. similarly, limiting can occur near full-scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc , as shown in figure 5 c. no full-scale limiting can occur if v ref is less than v cc C fse. offset and linearity are defined and tested over the region of the dac transfer function where no output limiting can occur.board layout the pc board should have separate areas for the analog and digital sections of the circuit. a single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. this keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. the resistance from the ltc2631 gnd pin to the ground plane should be as low as possible. resistance here will add directly to the effective dc output impedance of the device ( typically 0.1). note that the ltc2631 is no more susceptible to this effect than any other parts of this type; on the con - trary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. another technique for minimizing errors is to use a sepa- rate power ground return trace on another board layer. the trace should run between the point where the power supply is connected to the board and the dac ground pin. thus the dac ground pin becomes the common point for analog ground, digital ground, and power ground. when the ltc2631 is sinking large currents, this current flows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. it is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. when doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. downloaded from: http:///
ltc2631 24 2631fc for more information www.linear.com/ltc2631 operation figure 4. typical ltc2631 input waveform?programming 12-bit dac output for full-scale ack ack 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 2631 f04 ack start x = dont care stop full-scale voltage zero-scale voltage sda a6 a5 a4 a3 a2 a1 a0 scl v out c2 c3 c3 c2 c1 c0 x x x x c1 c0 x x x x ack command d11 d10 d9 d8 d7 d6 d5 d4 ms data d3 d2 d1 d0 x x x x ls data a6 a5 a4 a3 a2 a1 a0 w slave address downloaded from: http:///
ltc2631 25 2631fc for more information www.linear.com/ltc2631 operation figure 5. effects of rail-to-rail operation on a dac transfer curve (shown for 12-bits) ( a) overall transfer function ( b) effect of negative offset for codes near zero ( c) effect of positive full-scale error for codes near full-scale 2631 f05 input code (b) output voltage negative offset 0v 0v 2,048 0 4,095 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positivefse downloaded from: http:///
ltc2631 26 2631fc for more information www.linear.com/ltc2631 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 1.50 C 1.75 (note 4) 2.80 bsc 0.22 C 0.36 8 plcs (note 3) datum a 0.09 C 0.20 (note 3) ts8 tsot-23 0710 rev a 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref pin one id note:1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.40 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637 rev a) downloaded from: http:///
ltc2631 27 2631fc for more information www.linear.com/ltc2631 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number c 11/13 updated ts8 package drawing to rev a 26 (revision history begins at rev c) downloaded from: http:///
ltc2631 28 2631fc for more information www.linear.com/ltc2631 ? linear technology corporation 2008 lt 1113 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2631 related parts typical application part number description comments ltc1663 single 10-bit v out dac in sot-23 v cc = 2.7v to 5.5v, 60a, internal reference, smbus interface ltc1669 single 10-bit v out dac in sot-23 v cc = 2.7v to 5.5v, 60a, internal reference, i 2 c interface ltc2360/lt2362/ ltc2365/ltc2366 12-bit sar adcs in tsot23-6/tsot23-8 packages 100ksps/250ksps/500ksps/1msps/3msps output rates ltc2450/ltc2452 16-bit single-ended/differential delta sigma adcs spi interface, tiny dfn packages, 60hz output rate ltc2451/ltc2453 16-bit single-ended/differential delta sigma adcs i 2 c interface, tiny dfn and tsot23-8 packages, 60hz output rate ltc2600/ltc2610/ltc2620 octal 16-/14-/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2601/ltc2611/ltc2621 single 16-/14-/12-bit v out dacs in 10-lead dfn 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2602/ltc2612/ltc2622 dual 16-/14-/12-bit v out dacs in 8-lead msop 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2604/ltc2614/ltc2624 quad 16-/14-/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2605/ltc2615/ltc2625 octal 16-/14-/12-bit v out dacs with i 2 c interface 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, i 2 c interface ltc2606/ltc2616/ltc2626 single 16-/14-/12-bit v out dacs with i 2 c interface 270a per dac, 2.5v to 5.5v supply range, rail-to-rail output, i 2 c interface ltc2609/ltc2619/ltc2629 quad 16-/14-/12-bit v out dacs with i 2 c interface 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output with separate v ref pins for each dac ltc2630 single 12-/10-/8-bit v out dacs with 10ppm/c reference in sc70 180a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, rail-to-rail output, spi interface ltc2640 single 12-/10-/8-bit spi v out dacs with 10ppm/c reference in thinsot 180a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, selectable external reference mode, rail - to - rail output, spi interface programmable 5v output sdascl ca0 0.1f v out = 5v v cc ref v out i 2 c bus ltc2631a -lm12 2631 ta03 C + ltc2054 gnd ref_sel 83 2 1 4 5 6 7 5v ca0 5v C10v 10v 5 4 6 7 89 10 12 3 5 43 1 2 lt1991 m9m3 m1 p1p3 p9 v ee v cc out ref 0.1f 0.1f 0.1f 1.7k 1.7k downloaded from: http:///

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